1. Field of the Invention
The present invention relates to solid-state memory devices used as a finite-state-engine, such as a programmable logic array and, more particularly, to such a finite-state-engine with latched fedback memory features.
2. Setting of the Invention
In prior art programmable logic arrays (PLAs), such as the type shown in U.S. Pat. 4,124,899, during the transformation process used in the operation of the finite-state equations stores therein, there is a large period of time when the signals are considered unstable. This instability can cause jumbled, nonsensical data to be used as inputs; therefore, the desired output could be considered "garbage." To solve the problem of potential signal instability, complex circuitry and logic must be used to ensure that at a given instant the exact data set (input signal) is used as input for each of the several components within the PLA. This complex circuitry and logic operates successfully but has the drawbacks of being time consuming to ensure its correctness and if any change is desired to be made in the finite-state-equations, a total reconstruction of the synchronization circuitry and logic is required.
There is a need for a simple solid state device that can be used in place of prior art PLAs and have the capability of being easily altered and could not require the complex synchronization circuitry and logic.